Looking for immediate Joiners.
DFX Job Description
Job openings are for DFT Functional Verification Engineers. The candidate should have knowledge of SOC level verification methodologies and object oriented programming. Understanding and knowledge of Design For Test is desired (not mandatory).
The successful candidate will be responsible for:
– Functional Verification and Debug of DFT features (e.g., Memory BIST with repair, Logic BIST, Boundary Scan) in an x86 processor SoC design that consists of multiple IP blocks delivered from many diverse teams.
– SoC level test plan creation and development
– Executing verification plan using System Verilog/ Verilog /C++ using both direct and Constrained Randomized verification methodology. Porting or creating portions of the SOC level DFT Functional verification environment. Stimulus writing (using System Verilog /C++) and debug, and regression cleanup.
– Creating & analyzing coverage metrics to ensure completeness.
– Experience in complex SOC verification
– Good knowledge of Verilog and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations. Experience with Verilog design and simulation is a must.
– Candidate preferably should have knowledge in DFT techniques such as JTAG /IEEE standards, MBIST and repair, LBIST, Boundary Scan etc
– Experienced with testbench creation and functional coverage with HVL’s such as System Verilog/Vera
– Experience with C++ is a plus
– Good working knowledge of UNIX/Linux and scripting languages (e.g., cshell, Perl)
– Team player with strong communication skills
Excellent skills in oral and written business communications in English
Note: Need Immediate candidate or with NP max. 15 days.
Salary: Not Disclosed by Recruiter
Industry:IT-Software / Software Services
Functional Area:IT Software – Embedded , EDA , VLSI , ASIC , Chip Design
Role Category:Programming & Design
Employment Type: Permanent Job, Full Time
System Verilog VERA SOC Verification DFT Perl Bist JTAG Object Oriented Programming Design C++ Functional Verification
Desired Candidate Profile:
UG: Any Graduate – Any Specialization
PG:Any Postgraduate – Any Specialization
Quess Corp Ltd (Magna Infotech)
Magna Infotech Pvt Ltd
Contact Company:Quess Corp Ltd (Magna Infotech)