3 – 7 yrs Malaysia
Candidates should have 3+ yrs of Experience in OVM UVM< System Verilog.
They should have Minimum 1 Year exp on GLS or PCIE or SATA or USB Protocols
Salary:INR 6,50,000 – 9,00,000 P.A.
Industry:Semiconductors / Electronics
Functional Area:Engineering Design , R&D
Role Category:Engineering Design
Design Verification OVM UVM SV System Verilog USB PCIE
UG: B.Tech/B.E. – Any Specialization, Electrical, Electronics/Telecommunication, Computers
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