Strong hands-on experience with –
1. Synthesis, Floor planning, power planning, placement, timing optimization, clock tree synthesis.
2. Timing convergence using high speed design techniques with signal integrity & EM/IR.
3. Run equivalence checks across gates-to-gates as design progresses.
4. Physical design verification.
EDA Tool Expertise: Encounter Digital Implementation System, PrimeTime-SI, StarXT, Calibre, Formality, Calibre.
Good scripting skills (perl, tcl).
Excellent communication, presentation and technical writing skills,
On-time execution and Quality mindset
Salary: Not Disclosed by Recruiter
Industry:Semiconductors / Electronics
Functional Area:IT Software – Embedded , EDA , VLSI , ASIC , Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Floor Planning Physical Design STA Placement RTL Synthesis IC Compiler Netlist to GDS RTL to GDS PnR P&R Timing Digital Design ASIC Design IP Design Prime Time Gold Time place route
Desired Candidate Profile
UG: Any Graduate – Any Specialization, B.Tech/B.E. – Any Specialization
PG:M.Tech – Any Specialization, M.Sc – Any Specialization
Doctorate:Any Doctorate – Any Specialization, Doctorate Not Required
Please refer to the Job description above
Physical Design Engineers for multiple positions
Product based semiconductor MNCs
View Contact Details:
Recruiter Name:Sheshagiri Rao
Email Address:[email protected]