DFT engineer with good analyzing capabilities with the below skills : Scan insertion & ATPG
Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive).
Familiarity with WGL/TDL file formats.
Good skills in Scan compression techniques and Logic BIST.
Exposure to Memory BIST insertion tools (Preferably LogicVision MBIST).
Good experience in Boundary Scan, JTAG concepts, Core testing using P1500.
Should have basic understanding of Tester requirements.
Should be good at doing synthesis and timing (RC and PT/Tempus).
Knowledge of formal verification using LEC.
Exposure to SoC level DFT will be a plus. -Experience on low power DFT is an added advantage.
Salary: Not Disclosed by Recruiter
Functional Area: IT Software – Embedded, EDA, VLSI, ASIC, Chip Design
Role Category: System Design/Implementation/ERP/CRM
Role: Functional Outside Consultant
Employment Type: Permanent Job, Full Time
Desired Candidate Profile:
Education:UG -B.Tech/B.E. – Any Specialization
Doctorate – Doctorate Not Required
Cyient is a global provider of engineering, data analytics, networks and operations solutions. We collaborate with our clients to achieve more and shape a better tomorrow.
With decades of experience, Cyient is well positioned to solve problems. Our solutions include product development and life-cycle support, process and network engineering, and data transformation and analytics. We provide expertise in the aerospace, consumer, energy, medical, oil and gas, mining, heavy equipment, semiconductor, rail transportation, telecom and utilities industries.
Strong capabilities combined with a global network of more than associates across 38 global locations enable us to deliver measurable and substantial benefits to major organizations worldwide.
For more information about Cyient, visit www.cyient.com.
Recruiter Name:Sudhir Kakinada
This post was last modified on September 4, 2017, 5:00 pm